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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">GICD_TYPER2, Interrupt Controller Type Register 2</h1><p>The GICD_TYPER2 characteristics are:</p><h2>Purpose</h2>
        <p>Provides information about which features the GIC implementation supports.</p>
      <h2>Configuration</h2><p>This register is present only when FEAT_GICv4p1 is implemented. Otherwise, direct accesses to GICD_TYPER2 are <span class="arm-defined-word">RES0</span>.</p>
        <p>When <a href="ext-gicd_ctlr.html">GICD_CTLR</a>.DS == 0, this register is Common.</p>
      <h2>Attributes</h2>
        <p>GICD_TYPER2 is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="23"><a href="#fieldset_0-31_9">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-8_8">nASSGIcap</a></td><td class="lr" colspan="1"><a href="#fieldset_0-7_7">VIL</a></td><td class="lr" colspan="2"><a href="#fieldset_0-6_5">RES0</a></td><td class="lr" colspan="5"><a href="#fieldset_0-4_0">VID</a></td></tr></tbody></table><h4 id="fieldset_0-31_9">Bits [31:9]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-8_8">nASSGIcap, bit [8]</h4><div class="field">
      <p>Indicates whether SGIs can be configured to not have an active state.</p>
    <table class="valuetable"><tr><th>nASSGIcap</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>SGIs have an active state.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>SGIs can be globally configured not to have an active state.</p>
        </td></tr></table>
      <p>This bit is <span class="arm-defined-word">RES0</span> on implementations that support two Security states.</p>
    </div><h4 id="fieldset_0-7_7">VIL, bit [7]</h4><div class="field">
      <p>Indicates whether 16 bits of vPEID are implemented.</p>
    <table class="valuetable"><tr><th>VIL</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>GIC supports 16-bit vPEID.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>GIC supports GICD_TYPER2.VID + 1 bits of vPEID.</p>
        </td></tr></table></div><h4 id="fieldset_0-6_5">Bits [6:5]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-4_0">VID, bits [4:0]</h4><div class="field"><p>When GICD_TYPER2.VIL == 1, the number of bits is equal to the bits of vPEID minus one.</p>
<p>When GICD_TYPER2.VIL == 0, this field is <span class="arm-defined-word">RES0</span>.</p></div><h2>Accessing GICD_TYPER2</h2><h4>GICD_TYPER2 can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>GIC Distributor</td><td>Dist_base</td><td><span class="hexnumber">0x000C</span></td><td>GICD_TYPER2</td></tr></table><p>Accesses on this interface are <span class="access_level">RO</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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